1. Field of the Invention
The present invention relates to a method for the formation of contact holes in the semiconductor integrated circuit, and more particularly, to a method for the formation of contact holes in the semiconductor integrated circuit, in which contact holes are formed through from the region on the source/drain region (hereinafter called "S/D region") to the region on the field insulating film adjacent to the S/D region, then through those contact holes the interconnection layer is connected to the S/D region.
2. Description of Prior Art
In the semiconductor integrated circuit, particularly in the SRAM (Static Random Access Memory), the insulated gate field effect transistors which are formed on both sides of the field insulating film of isolation region are connected by interconnection. For such connection, the contact holes are formed on the S/D regions of transistors. However, in case of making the S/D regions and the contact holes fine to advance the integration level, it becomes difficult to secure a sufficient area of the contact hole. In such a case, to secure the sufficient area, the contact hole is formed through from the region on the S/D region to the region on the field insulating film adjacent to the S/D region.
In order to contact the S/D region and the interconnection layer each other securely, the natural oxide on the surface of S/D region in the contact hole must be removed before the interconnection layer is formed. As its process, for example, there is a method called "vapor etching" using gaseous etchant. In such a process, outside the region where the contact hole is formed, the insulating film must remain to hold the insulation between the semiconductor substrate and the interconnection layer, but while vapor-etching such insulating film is exposed to the etchant, so there is a risk that the insulating film is damaged. To prevent such damage, for example, as illustrated in a patent document of the Japanese unexamined publication (KOKAI) 63-196064, a protecting film is formed on the insulating film except the region where the contact hole is formed.
When the above technique in the patent document of the Japanese unexamined publication (KOKAI) 63-196064 is applied to the case where the field insulating film appears in the contact hole, the insulating film is protected by the protecting film while the natural oxide is etched. However, the field insulating film exposed in the contact hole is etched excessively, so that the field insulating film itself might become thin, or the semiconductor substrate under the field insulating film might come out. In this case, when the interconnection layer is formed in the contact hole, there come some problems that the semiconductor substrate under the field insulating film might be inverted, or the S/D regions of the transistors on both sides of the field insulating layer might short. To prevent such short-circuit, it might be considered to adjust the etching rate. However, since the etching rate of the substance to be etched in the contact hole depends on the opening area of contact hole, it is not possible to obtain the etching rate to be uniform throughout the semiconductor substrate.